The present invention relates generally to content addressable memory (CAM) devices.
The Internet Protocol (IP) is used to relay packets of information in the Internet. IPv4 is a common addressing scheme that includes a 32-bit binary address represented in dotted decimal notation of the form M.N.O.P where M, N, O, and P are decimal values ranging from 0 to 255. The 32-bit address is segmented into Network and Host address fields and can be implemented in a classfull or classless model. In the classfull model, the IPv4 address is segmented into Class A, B, and C addresses each having a number of the 32 bits designated for the Network address field and the remainder of the 32 bits designated for the Host address field. The classfull scheme has generally resulted in wasted addresses and large IP address tables.
In the Classless Inter Domain Routing (CIDR) scheme, the traditional classfull segmentation is replaced with an IP address that has a generalized network prefix that generally ranges from 13 to 27 bits of the 32-bit IPv4 address. The network prefix or mask indicates the number of left-most contiguous bits in the IP address that are used to filter an IP address in a routing table. That is, the network prefix indicates the number of higher-order or left-most contiguous bits in the IP address that participate in an address comparison with the routing table. A CIDR address is typically written as the IPv4 address followed by xe2x80x9c/Zxe2x80x9d where Z indicates the prefix length in decimal notation. An IPv4 address followed by the prefix length /Z will hereafter be referred to as axe2x80x9cCIDR addressxe2x80x9d.
Routing table entries typically include the IP addresses and their corresponding prefixes. FIG. 1 shows a routing table having five CIDR addresses where an xe2x80x9cXxe2x80x9d entry indicates that these bits do not participate in a search with a search key. Any search key whose most significant eight bits have the decimal equivalent of 168 will potentially match all of the entries. For example, 168.0.0.0/8, 168.64.0.0/12, and 168.69.0.0/16 all match the search key of 168.69.43.100. However, it is desirable that a search would yield 168.69.0.0/16 as this entry has the largest number of unmasked most significant bits that match the search key.
Routing table entries are typically stored in a CAM device that can rapidly perform a search against the search key to locate the longest matching CIDR address. As there may be multiple matching entries, CAM devices typically include a priority encoder that selects a matching entry that has the lowest logical or numerical address in the CAM array. For example, if a CAM device stores the table of FIG. 1 in a prearranged order such that 168.69.62.0/24 is stored in a lower logical address than 168.0.0.0/8 (as shown in FIG. 1), then the CAM device would correctly indicate the longest matching CIDR address as 168.69.0.0/16. If, however, the entries were stored in an arbitrary manner as indicated in FIG. 2, then the CAM device would incorrectly indicate a match of 168.64.0.0/12 as this entry is located at a lower logical address than 168.69.0.0/16 and 168.0.0.0/8. 168.64.0.0/12 is not, however, the longest matching CIDR address. Thus, CIDR addresses are generally pre-sorted or prearranged prior to entry into a CAM device such that the CIDR address with the longest network prefix is located in the lowest logical address of the CAM device, and the CIDR address with the shortest network prefix is located in the highest logical address of the CAM device.
A considerable amount of time is generally required to prearrange all of the CIDR address entries prior to loading the entries into a CAM device. Additionally, a considerable amount of time and overhead is also generally required to maintain the order of the routing table when entries are deleted or overwritten, or when new entries are to be added. A typical routine for updating the table includes a bubble sorting algorithm that generally takes many clock cycles to read the entries in the table, compare the entries, and then reload the table. Another approach segments the CAM array into separately addressable hierarchical blocks that each store entries associated only with certain prefixes. However, this approach has the disadvantages of wasting unused CAM locations, and of limiting the number of entries into any one block. This approach also requires that the CAM array be loaded with CIDR addresses in a prearranged fashion.
A method and apparatus for determining a longest prefix match in a content addressable memory (CAM) device is described. The CAM device includes a CAM array that may be arbitrarily loaded with CIDR addresses that are not prearranged prior to their entry into the CAM device. For one embodiment, the CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), prefix match lines, and prefix logic circuits for comparing the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix among the CAM locations that match the search key, regardless of where the matching locations are logically located in the CAM array. The longest prefix is then compared against the prefix mask data stored in the mask cells to determine the location in the CAM array that stores the CIDR address corresponding to the longest prefix. The CAM index or address of the matching CIDR address may then be output from the CAM device. Additionally and/or alternatively, additional or associated data stored at the CAM index may be accessed. The additional or associated data may be, for example, routing information for the stored CIDR address.
A method and apparatus for determining a longest prefix match in a segmented content addressable memory (CAM) device is also described. The CAM device includes multiple CAM array blocks that each may be arbitrarily loaded with CIDR addresses. For one embodiment, each CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), and prefix logic circuits for comparing the logical state of the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix in each CAM array block from among CAM entries that match the search key. The longest prefixes from each block are provided to compare circuitry that determines which of the longest prefixes is the longest for the entire CAM device. A block select circuit selects the CAM array block that stores the longest prefix for the entire CAM device for comparison with the prefix mask data in that CAM array block. The CAM index or address of the matching location may then be output from the CAM device. By restricting the search of the device-level longest prefix to only one CAM array block, power drawn by this comparison is reduced over searching all CAM array blocks in parallel.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description, which follows below.